The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to the use of alignment marks to facilitate the three-dimensional integration of integrated circuit (IC) devices.
The packaging density in the electronics industry continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) wafer-to-wafer stacking technology substantially contributes to the device integration process. Typically, a semiconductor wafer includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a semiconductor substrate. In order to form a 3D wafer stack, two or more wafer substrates are placed on top of one other and bonded. A top layer of the bonded wafer stack may be connected to a bottom layer of the wafer stack utilizing through silicon interconnects or vias.
3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (SOC) solutions. In addition, the 3D wafer stacking technology may provide other functionality to the chip. For instance, after being formed, the 3D wafer stack may be diced into stacked dies or chips, with each stacked chip having multiple tiers (i.e., layers) of integrated circuitry. SOC architectures formed by 3D wafer stacking can enable high bandwidth connectivity of products such as, for example, logic circuitry and dynamic random access memory (DRAM), that otherwise have incompatible process flows. At present, there are many applications for 3D wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.
When creating wafer substrates to form a 3D stack, additional processing may be required on the backside plane of the wafer substrate, either prior to or after the completion of the bonding process. Since the backside plane is initially without any features, it effectively is a virgin silicon surface. Alignment of features formed on the unpatterned backside plane to features on the front side of the wafer substrate is critical to functionality of 3D interconnected structures, particularly when utilizing a via-last integration scheme that requires accurate alignment to form interconnections to existing features that are not visible after face-to-face substrate bonding. Present alignment methodologies known in the art used to enable backside first-level alignment require specialized hardware, additional processing, and add micron-scale variability and alignment inaccuracy to the manufacturing process. To enable high-density 3D structures, improved accuracy and cost-effective alignment processes are required.